1. Field of the Invention
The present invention relates to a semiconductor memory device, for example, an FBC (Floating Body Cell) memory device for storing data by accumulating majority carriers in floating bodies of field effect transistors.
2. Related Art
In recent years, there has been known an FBC memory device as a semiconductor memory device expected to replace a 1T (Transistor)-1C (Capacitor) DRAM. The FBC memory device includes memory cells each configured so that an FET (Field Effect Transistor) including a floating body (hereinafter, also “body”) formed on an SOI (Silicon On Insulator) is formed and so that data “1” or “0” is stored in the FET according to the number of majority carriers accumulated in the body. A state in which the number of holes (majority carriers) in the body is small corresponds to data “0” and a state in which the number of holes (majority carriers) in the body is large corresponds to data “1”.
In a conventional FBC memory device using n-type FETs as memory cells, voltages of word lines and source lines are lowered to an equal negative voltage so as to write data “0” to the memory cells. Accordingly, a forward bias is applied to junctions between bodies and sources and holes accumulated in the respective bodies are discharged to the respective sources (P. Malinge et al., “An 8 Mbit DRAM Design Using a 1TBulk Cell” 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp. 358-361, June 2005 (non-patent document 1)). The reason for setting the voltages of the source lines and the word lines to the equal negative voltage is to avoid formation of channels in the memory cell so as not to carry a current between the sources and the drains. By so setting, write current is reduced.
To write data “0” to the memory cells, there is known a method of setting the voltage of the word lines and the bit lines to a high voltage (P. Fazan et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), September 2002, pp. 99-102 (non-patent document 2)). With this method, a voltage of the word lines is set higher than that of the bit lines, thereby causing transistors to operate in linear regions. As a result, potentials of the bodies are raised and a forward bias is applied to the junctions between the bodies and the source without causing impact ionization. The forward bias discharges the holes accumulated in the bodies to the sources.
With these conventional techniques, the forward bias applied to the junctions between the sources and the bodies is not large. Due to this, the conventional techniques have a disadvantage in that many holes remain in the bodies. If many holes remain in the bodies, a difference ΔVth (=Vth0−Vth1) between a threshold voltage Vth0 of the memory cells storing therein data “0” (hereinafter, also “0” cells) and a threshold voltage Vth1 of the memory cells storing therein data “1” (hereinafter, also “1” cells) becomes small.
Generally, many memory cells are present in a semiconductor memory device and threshold voltages of the memory cells are always irregular. If the threshold voltage difference ΔVth is smaller, the number of defective memory cells that cannot be detected by sense amplifiers becomes larger due to the influence of the irregularity among the threshold voltages.